1. Field of the Invention
The present invention relates to a delta sigma modulator which includes an integration circuit and a quantizer connected in cascade, each as a component thereof, and also comprises a first power source terminal connected to the former-stage integration circuit, and a second power source terminal connected to the latter-stage quantizer to allow a reduction in power consumption without degrading a SNR (Signal to Noise Ratio).
The present invention also relates to a delta sigma modulator which includes a first integration circuit and a second integration circuit connected in cascade, each as a component thereof, and also comprises a first power source terminal connected to the former-stage first integration circuit and a second power source terminal connected to the latter-stage second integration circuit to allow a reduction in power consumption without degrading the SNR.
The present invention further relates to a delta sigma modulator which has a plurality of delta sigma modulation type quantization loops connected in cascade in multiple stages, and also comprises a first power source terminal connected to a first integration circuit composing the first-stage delta sigma modulation type quantization loop, and a second power source terminal connected to a second integration circuit composing second and subsequent delta sigma modulation type quantization loops to allow a reduction in power consumption without degrading the SNR.
2. Description of the Related Art
A system using a delta sigma modulator has been conventionally known, and used in an AD converter for digital audio equipment or the like. When the system is used in portable equipment, in particular, low power consumption is considered to be important.
Conventionally, an oversampling AD converter often referred to as a delta sigma AD converter has been well known. The delta sigma AD converter digitizes an analog signal at an extremely high oversampling rate, and simultaneously performs noise shaping for shifting noise to a high frequency range, and a digital filtering process after the noise shaping. This allows the delta sigma AD converter to implement an effective resolution higher than a quantized output of a delta sigma modulator. Thereafter, the effective sampling rate is returned to a Nyquist rate using decimation.
The noise shaping is a technique which lowers the level of quantization noise showing a uniform-level frequency distribution in a low frequency range in which an original signal is present by an differential/integral operation in accordance with delta sigma modulation without changing the frequency characteristics of the original signal, and conversely raises the level of quantization noise in a high frequency range in which a sampling frequency is present.
The effect of the noise shaping is larger as the order of a delta sigma modulation is higher, i.e., the number of stages of integrators composing a delta sigma modulator is larger. Accordingly, the noise shaping effect of a second-order delta sigma modulator is higher than that of a first-order delta sigma modulator.
FIG. 13 shows a structure of a single-loop second-order delta sigma modulator as a conventional embodiment. A delta sigma modulator 1 comprises first and second integration circuits 10 and 11, amplifiers 20 and 21 each having an amplification factor a1, an amplifier 22 having an amplification factor a2, a quantizer 2, adders/subtractors 3 and 4, and DA converters 30 and 31. The delta sigma modulator 1 operates with a power source voltage VDD1 supplied from a power source terminal 600.
The first integration circuit 10 receives a signal obtained by subtracting, from a signal obtained by passing an analog input signal Ain through the amplifier 20, a signal obtained by passing a feedback reference voltage (positive voltage+Vr1 or negative voltage−Vr1) generated from the DA converter 30 through the amplifier 21 by means of the adder/subtractor 3.
The second integration circuit 11 receives a signal obtained by subtracting, from an output of the first integration circuit 10, a signal obtained by passing a feedback reference voltage (positive voltage+Vr1 or negative voltage−Vr1) generated from the DA converter 31 through the amplifier 22 by means of the adder/subtractor 4.
The quantizer 2 quantizes an output of the second integration circuit 11 to a 1-bit digital output signal Dout.
The DA converters 30 and 31 generate the feedback reference voltage (positive voltage+Vr1 or negative voltage−Vr1) mentioned above from the 1-bit digital output signal Dout of the quantizer 2.
Typically, the 1-bit digital output signal Dout of the delta sigma modulator 1 is inputted to a digital filter circuit for the retrieval of a needed signal band. The delta sigma modulator 1 composes an AD converter.
As a result, when the digital output signal Dout of the delta sigma modulator 1 is normalized such that a digital full scale value equals 1, it can be given by the following transmission function:
                                                        Dout              ≅                            ⁢                                                Ain                                      2                    ·                                          Vr                      1                                                                      +                                                                                                      ⁢                                                                                          (                                              1                        -                                                  Z                                                      -                            1                                                                                              )                                        2                                    ⁢                                      Q                    ·                    2                    ·                                          Vr                      1                                                                                        2                  ·                                      Vr                    1                                    ·                                      [                                          1                      -                                                                        (                                                      2                            -                                                          a                              2                                                                                )                                                ⁢                                                  Z                                                      -                            1                                                                                              +                                                                        (                                                      1                            +                                                          a                              1                                                        -                                                          a                              2                                                                                )                                                ⁢                                                  Z                                                      -                            2                                                                                                                ]                                                                                                                          =                            ⁢                                                Ain                                      2                    ·                                          Vr                      1                                                                      +                                                                                                    (                                                  1                          -                                                      Z                                                          -                              1                                                                                                      )                                            2                                        ⁢                    Q                                                        1                    -                                                                  (                                                  2                          -                                                      a                            2                                                                          )                                            ⁢                                              Z                                                  -                          1                                                                                      +                                                                  (                                                  1                          +                                                      a                            1                                                    -                                                      a                            2                                                                          )                                            ⁢                                              Z                                                  -                          2                                                                                                                                                                            Expression        ⁢                                  ⁢        1            
where the digital full scale value corresponds to the voltage±Vr1 of an analog value, and Q represents quantization noise generated in the quantizer 2.
A description will be given to a specific circuit structure for implementing the delta sigma modulator 1 of FIG. 13 with reference to FIG. 14.
FIG. 14 is a circuit diagram showing an example of the specific circuit structure of a single-loop second-order delta sigma modulator 101 using a switched capacitor circuit. The first and second integration circuits 10 and 11, the DA converters 30 and 31, and the adders/subtractors 3 and 4 of FIG. 13 are composed of the switched capacitor circuit comprising switches 41 to 52 and 61 to 72, capacitors C11 to C14 and C21 to C24, operational amplifiers 6 and 7, and buffers 5 and 8 in FIG. 14. VDD1 is a power source voltage supplied to the second-order delta sigma modulator 101. 601 is a power source terminal.
The analog input signal Ain is integrated by the operational amplifier 6 using the reference voltage Vr1 as well as charging and discharging between the capacitors C11 and C14.
A feedback signal is processed as follows. The digital output signal Dout is converted by the buffer circuit 5 to digital signals S1p and S1n. Then, by turning ON/OFF the switches 46 and 50 in accordance with the levels of the digital signals S1p and S1n, a DA conversion using the reference voltage Vr1 and a zero voltage is performed. The DA converted voltage is integrated by the operational amplifier 6 using the charging and discharging between the capacitors C12 and C13.
In this manner, the first integration circuit 10 and the DA converter 30 are constructed. The amplification factor a1 of the amplifier 20 shown in FIG. 13 corresponds to the capacitance ratio C11/C14, while the amplification factor a1 of the amplifier 21 shown in FIG. 13 corresponds to the capacitance ratios C12/C14 and C13/C14.
Next, the output signal of the operational amplifier 6 is integrated by the operational amplifier 7 using the reference voltage Vr1 as well as the charging and discharging between the capacitors C21 and C24.
The feedback signal is processed as follows. The digital output signal Dout is converted by the buffer circuit 5 to the digital signals S1pand S1n. Then, by turning ON/OFF the switches 66 and 70 in accordance with the levels of the digital signals S1pand S1n, a DA conversion using the reference voltage Vr1 and a zero voltage is performed. The DA converted voltage is integrated by the operational amplifier 7 using the charging and discharging between the capacitors C22 and C23.
In this manner, the second integration circuit 11 and the DA converter 31 are constructed. The amplification factor a2 of the amplifier 22 shown in FIG. 13 corresponds to the capacitance ratios C22/C24 and C23/C24.
The output signal of the operational amplifier 7 is quantized by a comparator 12, and outputted as the 1-bit digital signal Dout. The comparator 12 corresponds to the quantizer 2 of FIG. 13.
The buffer circuit 5 outputs the digital signals S1pand S1n which are each in-phase or anti-phase with the 1-bit digital output signal Dout of the delta sigma modulator 101. The switches 46 and 66 are under the ON/OFF control of the digital signal S1n. The switches 50 and 70 are under the ON/OFF control of the digital signal S1p, which is opposite to the ON/OFF control over the switches 46 and 66.
The buffer circuit 8 receives a control clock for the switched capacitor circuit, and outputs digital signals φ1p and φ1n which are each in-phase or anti-phase with the control clock. The switches 41, 44, 45, 48, 51, 52, 61, 64, 65, 68, 71 and 72 are under the ON/OFF control of the digital signal φ1p. The switches 42, 43, 47, 49, 62, 63, 67, and 69 are under the ON/OFF control of the digital signal φ1n, which is opposite to the control over the switches 41, 44, 45, 48, 51, 52, 61, 64, 65, 68, 71 and 72.
As shown in FIG. 15, the buffer circuit 5 comprises an inverter IN1 composed of a P-channel transistor 81A and an N-channel transistor 82A, an inverter IN2 composed of a P-channel transistor 81B and an N-channel transistor 82B, and an inverter IN3 composed of a P-channel transistor 81C and an N-channel transistor 82C. A signal which is in-phase with the signal inputted to an input terminal IN is outputted from an output terminal OUTp, while a signal which is anti-phase with the signal inputted to the input terminal IN is outputted from an output terminal OUTn.
The buffer circuit 8 has the same structure as that of the buffer circuit 5.
The switches 41 to 52 and 61 to 72 are each composed of, e.g., an N-channel transistor 83 shown in FIG. 16, and intermittently interrupts (ON/OFF) a signal with the timing of a signal CLK (clock) inputted to the gate thereof. The signal CLK is supplied from each of the buffer circuits 5 and 8.
FIG. 17 shows an example of respective circuits which implement the operational amplifiers 6 and 7, and the comparator 12. These circuits are composed of P-channel transistors 84A to 84C, N-channel transistors 85A and 85B, and current sources 86A and 86B.
The reference voltage Vr1 is supplied by, e.g., dividing the power source voltage VDD1 with resistors 405A and 405B, and amplifying the divided voltage with an operational amplifier 406, as shown in FIG. 18.
Thus, the delta sigma modulator shown in FIG. 13 is composed of the switched capacitor circuit.
As a CMOS circuit has been increasingly scaled down from 0.35 μm to 0.18 μm, and to 0.13 μm, the operation voltage thereof has also been reduced from 3.3 V to 1.8 V, and to 1.2 V. To reduce the power consumption of a delta sigma modulator, it is effective to minimize the power source voltage thereof, and operate the delta sigma modulator.
However, when the delta sigma modulator is operated with a lowered power source voltage, the dynamic range of the circuit is narrowed so that it is necessary to simultaneously reduce the amplitude of the input signal as well as the feedback reference voltage. As a result, the SNR (Signal to Noise Ratio) during an AD conversion deteriorates. In addition, a voltage for driving the MOS switch of the switched capacitor circuit also lowers to lead to the problem that the ON resistance of the switch increases, and the turning ON/OFF of the switch becomes difficult. Thus, it is not easy to lower the power source voltage of an analog circuit.
A description will be given hereinbelow to the ON resistance of the switch mentioned above. The ON resistance of the switch of FIG. 16 can be given by:Ron≈1/(μ*Cox*W/L*(Vgs−Vt))where μ is a mobility, Cox is the thickness of a gate oxide film, W is a gate width, L is a gate length, Vgs is a gate-source drive voltage, and Vt is a threshold. Accordingly, when the voltage Vgs decreases, the ON resistance Ron increases.
Even microfabrication processes using design rules of 0.18 μm or below have many examples in which a transistor adapted to perform a 3.3 V operation by varying the thickness of the gate oxide film is embedded for an external interface (I/F). As a result, there is disclosed a method which lowers power consumption by using a 3.3 V transistor for an analog circuit such as a delta sigma modulator, and operates, with a low power source voltage, only a digital circuit such as a digital filter connected in a stage subsequent thereto or the like (see Japanese Unexamined Patent Publication No. HEI 6-283980).